SOCC 2021 Tutorial Day Program

September 14, 2021

* download of session recordings available via EDAS for registered attendees only

 Track A - Virtual Room 1 - Session Chair: Lan-Da Van0

Toward Secure Deep Learning Deployment 

Presenters:

Dr. Wenye Liu, Postdoctoral Researcher, School of Electrical and Electronic Engineering Nanyang Technological University, Singapore
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Prof. Chip-Hong Chang, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
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Abstract: This tutorial will expose the security flaws and weaknesses that can impact the integrity and confidentiality of the deep learning hardware systems. Model integrity is a primary pillar for artificial intelligence (AI) trust to ensure that the system deliver and maintain the desirable quality of service and are free from unauthorized deliberate or inadvertent manipulation of the system throughout the lifetime of their deployment. A superior and well-trained deep neural network (DNN) classifier requires heavy investment on large labelled training dataset, human expertise and enormous computing power. It is not only an intellectual property (IP) of high market value but also consists of private and sensitive information. Unfortunately, existing DNN hardware implementations mainly focus on throughput and energy efficiency optimization, which can unintentionally introduce exploitable vulnerabilities. The situation is aggravated by the trend of deploying trained model on edge computing devices and leasing of AI models on cloud platform. This paradigm extends the attack surface and opens out an uncharted territory of security threats. Attack vectors such as rowhammer, fault injection and side-channel attacks bring serious challenges on cloud and endpoint devices. In view of the severe consequence of potentially degraded system quality, reliability and performance, as well as leakage of model IP and private data, some solutions have been proposed to enhance the security and trust of DNN hardware. These defenses include resilient hardware design to mitigate the attack impact, obfuscation methods to lock the model IP with specific key, operation masking to remove the dependencies between the processed data and side-channel signatures. This tutorial will focus on deployment threats, hardware attack vectors, reverse engineering of model parameters and inference data recovery on cloud and edge deep learning implementations. Recent efforts in developing resilient and trustworthy DNN hardware and their limitations are also presented and discussed.

Biographies of Presenters: 

Wenye Liu received the B.S. degree in microelectronics from Shenzhen University, China, in 2014, the B.S. degree in physics from Umea University, Sweden, in 2014 and the M.S. degree in IC design engineering from Hong Kong University of Science and Technology, in 2015. He has just completed his Ph.D thesis with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore and working as a postdoctoral researcher in Professor Chip-Hong Chang’s research group. His areas of research include hardware security, machine learning accelerator, fault injection attacks and so on. He has published 10 IEEE Journal and Conference papers, including Transactions on Information Forensics and Security (TIFS), Transactions on Industrial Electronics (TIE), Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), Design Automation Conference (DAC), International Symposium on Circuits and Systems (ISCAS), and Asian Hardware Oriented Security and Trust Symposium (AsianHOST). He received the DAC 2020 young fellows poster presentation award. He is an active member of IEEE and CAS society. He has served as a reviewer for ISCAS, AsianHOST, Attacks and Solutions in Hardware Security (ASHES), IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and etc. since 2018.

Chip-Hong Chang received the B.Eng. (Hons.) degree from the National University of Singapore, in 1989, and the M. Eng. and Ph.D. degrees from Nanyang Technological University (NTU), Singapore, in 1993 and 1998, respectively. He served as a Technical Consultant in industry prior to joining the School of Electrical and Electronic Engineering (EEE), NTU, in 1999, where he is currently an Associate Professor. He holds joint appointments with the university as Assistant Chair of Alumni of the School of EEE from June 2008 to May 2014, Deputy Director of the Center for High Performance Embedded Systems from 2000 to 2011, and Program Director of the Center for Integrated Circuits and Systems from 2003 to 2009. He has coedited 5 books, 13 book chapters, more than 100 international journal papers (more than 70 are in IEEE Journals) and more than 170 refereed international conference papers. He has been well recognized for his research contributions in hardware security and trustable computing, low-power and fault-tolerant computing, residue number systems, and digital signal and image processing. He has delivered several keynotes and more than 40 invited colloquia, including tutorials at the 2017 Asia and South Pacific Design Automation Conference (ASP-DAC 2017), the 2017 and 2021 IEEE International Symposium on Circuits and Systems (ISCAS 2017), and the Advance CMOS Technology Winter School (ACTS 2020).

Dr. Chang currently serves as the Senior Area Editor of IEEE Transactions on Information Forensic and Security (TIFS), and Associate Editor of the IEEE Transactions on Circuits and Systems-I (TCAS-I) and IEEE Transactions on Very Large Scale Integration (TVLSI) Systems. He also served in past as the Associate Editor of the IEEE TIFS and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) from 2016 to 2019, IEEE Access from 2013 to 2019, IEEE TCAS-I from 2010 to 2013, Integration, the VLSI Journal from 2013 to 2015, Springer Journal of Hardware and System Security from 2016 to 2020 and Microelectronics Journal from 2014 to 2020. He also guest edited eight journal special issues including IEEE TCAS-I, IEEE Transactions on Dependable and Secure Computing (TDSC), IEEE TCAD and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), of which four are related to hardware security. He has served key appointments in the organizing and technical program committees of more than 60 international conferences (mostly IEEE), including the General Co-Chair of 2018 IEEE Asia-Pacific Conference on Circuits and Systems and the inaugural Workshop Chair and Steering Committee of the ACM CCS satellite workshop on Attacks and Solutions in Hardware Security. He is the 2018-2019 IEEE CASS Distinguished Lecturer, a Fellow of the IEEE and the IET. 

Track B - Virtual Room 2 - Session Chair: Selçuk Köse

Design of Secure and Efficient Processing-In-Memory Systems for Large-Scale Applications

Presenters:

Prof. Md Tanvir Arafin, Morgan State University, USA.
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Prof. Zhaojun Lu, Huazhong University of Science and Technology, China
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Dr. Xueyan Wang, Beihang University, China
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Abstract: The cost of data movement and the performance gap between the CPU and main memory set a substantial price on the total computation cost of emerging data-intensive applications. Processing-in-memory (PIM) is one of the critical ideas that reduce this cost and performance gap by moving computation to (or near) the data. In-memory calculations such as arithmetic addition, subtraction, matrix multiplication, and fundamental logic operations have been demonstrated in SRAM, DRAM and other emerging non-volatile memory devices. These techniques have the potential to accelerate data-intensive applications and services substantially. However, the design of secure and efficient PIM systems requires further investigations on critical reliability and efficiency issues such as (1) the security challenges of the PIM implementations and (2) optimization of PIM-based accelerators for big-data applications (e.g., graph processing, machine learning algorithms, etc.). This tutorial will provide our insights on these problems through three presentations and one interactive panel discussion. The total length of the tutorial will be 120 minutes, including a 10-minute break. The three speakers are from academia with rich experience and solid track-record on security, hardware accelerator, and processing-in-memory research.

Biographies of Presenters:

Md Tanvir Arafinis an Assistant Professor at the ECE Department at Morgan State University. He received M.S., and Ph.D. degrees in Electrical and Computer Engineering from the University of Maryland, College Park, in 2016 and 2018. Dr. Arafin’s research focuses on hardware-based authentication, memory systems, and distributed neuromorphic computing. Dr. Arafin’s work has been published in several top-tier peer-reviewed journals and conferences, such as IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), ACM International Conference on Computer-Aided Design (ICCAD), and Asia and South Pacific Design Automation Conference (ASP-DAC). He won the IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST) best paper award in 2018.

Zhaojun Lu is an Assistant professor in the School of Cyber Science and Engineering, Huazhong University of Science and Technology, Wuhan, China. He was engaged in postdoctoral research at the University of Maryland, College Park, from 2018 to 2020. His research focuses on hardware security, vehicular ad-hoc network security and privacy, and artificial intelligence security with more than 600 citations.

Xueyan Wang is a postdoctoral research fellow in the School of Integrated Circuit Science and Engineering, Beihang University, Beijing, China. She received a Ph.D. degree in computer science and technology from Tsinghua University, Beijing, China, in 2018. From 2015 to 2016, she was a visiting scholar at the University of Maryland, College Park, MD, USA. Her current research interests include processing-in-memory architectures, A.I. chip, and hardware security. She has published important papers in top conferences and journals such as DAC and TCAD. She serves as a program committee member for venues of international conferences such as ASP-DAC, GLSVLSI, and SOCC.