Las Vegas, NV (hybrid)
September 14-16, 2021

Today’s fastest interconnects of systems or SoCs run at data rates in multi-gigahertz range, and these fast switching signals can generate considerable noise and radiation which degrade system performance.  Maintaining good signal integrity of these signals is very challenging as traces interconnecting SoCs on a printed circuit board (PCB) or cables interconnecting machine learning or cloud computing servers become very lossy transmission lines and cause excessive insertion loss. 

High speed interconnects are increasingly becoming a major “bottle neck” for advancing technology, especially when deploying advanced quantum computing systems to the mass market. 

The topics covered in this special session are:

  • Challenges in interconnecting high speed SoCs
  • Interconnects of high performance cloud based servers
  • Signal integrity issues related to transferring massive data sets to and reading the data from memory in machine learning systems
  • SERDES is the industry standard for transmitting/receiving up to 112Gbps data now.What will be the next serial interconnecting bus that can be implemented on a low cost FR4 printed circuit board?

 

Friday Sept. 17, 2021  
Session Chair: Thanh Tran, Rice University

Schedule

Title

Speaker

09:50-10:00AM EDT Chair's Welcome Address Prof. Thanh Tran, Rice University

1st: nVidia
10:00-10:30AM EDT

Challenges for Future High-Speed Interconnects within Systems Leveraging Advanced Packaging Techniques

Dr. Walker TurnerSenior Research Scientist, nVidia

2nd: Dell Technologies
10:30-11:00AM EDT

High-Speed Signal Integrity Challenges and Opportunities for Next Generation Technologies

Dr. Bhyrav Mutnury, Senior Distinguished Engineer and Global Team Lead, Dell EMC

11:00-11:10AM

Break

3rd: AMD
11:10-11:40AM EDT

Signal Integrity Outlook of Chiplet-Based Packaging

Dean Gonzales, AMD Analog Fellow

4th: Intel
11:40AM -12:10PM EDT

High-Speed Electrical I/O Interfaces and Interconnects from 112Gbps to 224Gbps

Dr. Peng Mike Li, Intel Fellow

Panel Discussion
12:20 - 12:50PM EDT

Challenges in High Speed SoC/System Interconnects

All speakers


Invited Talk # 1:

Challenges for Future High-Speed Interconnects within Systems Leveraging Advanced Packaging Techniques

Dr. Walker Turner, Nvidia Research, Durham, NC

Abstract: With the end of Moore’s Law, high-performance computational systems will need to embrace architectural and system-level changes to enable the continued performance growth required to meet future market demands. Large single-die processors will be replaced with multi-chip systems that leverage advanced packaging techniques such as 2.5D, 3D, and chiplet technologies. This imposes several challenges on the high-speed serial links that interconnect these board- and rack-scale systems, which need to provide ever-increasing off-chip bandwidths while consuming a fraction of total system power. This comes at a time when increasing the per-channel data-rate can no longer rely on the transistor-speed scaling that historically comes from newer technology nodes. Instead, future systems will need to embrace a co-optimization of both the high-speed circuitry and signaling channels, where a combination of package manufacturing improvements, higher-order modulation schemes, and advanced packaging techniques can help to achieve the necessary bandwidth and power targets.

Biography:

Walker Turner is a Senior Research Scientist at NVIDIA. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Florida in 2009, 2012, and 2015, respectively. In 2014, he was a contractor with the U.S. Army Research Laboratory developing wirelessly powered systems and integrated low-noise amplifiers for piezoelectric E-field sensors. He has been with NVIDIA since 2015, working in the Circuits Research Group in Durham, North Carolina. His research focuses on energy-efficient, high-speed signaling systems for on- and off-chip communication. He also joined North Carolina State University in 2019 as a Teaching, Assistant Professor, where he instructs an undergraduate microelectronics course.


Invited Talk # 2:

High-Speed Signal Integrity Challenges and Opportunities for Next Generation Technologies

Dr. Bhyrav Mutnury, Senior Distinguished Engineer and Global Team Lead, Dell EMC

Abstract: In this invited guest lecture Dr. Bhyrav Mutnury will talk about the challenges associated with high-speed signal integrity (SI) as it becomes exponentially complex with the doubling of signal speeds every generation. In this presentation, high-speed server design is used as an example to demonstrate the next generation SI challenges and potential opportunities to overcome these challenges. The presentation also discusses impact of loss, reflections and crosstalk on high-speed designs and ways to mitigate these parasitic effects. 

Biography:

Bhyrav Mutnury received the M.Sc. degree in electrical engineering, in 2002, and the Ph.D. in electrical engineering, in 2005 from the Georgia Institute of Technology, Atlanta, GA, USA.

He is a Senior Distinguished Engineer and Global SI Leader at Infrastructure Solutions Group at Dell Technologies where he is responsible for storage, network, rack, and blade server designs. He is driving the next generation high-speed interfaces and modeling methodologies at Dell. He has more than 21 years of progressive experience in system design with strong focus on electrical modeling, analysis and optimization of complex high speed servers.

Dr. Mutnury has authored and co-authored more than 80 refereed publications in various IEEE and non IEEE conferences. He has filed more than 180 invention disclosures.  He is an IEEE Fellow and the recipient of IEEE EMC Technical Achievement Award.


Invited Talk # 3:

Signal Integrity Outlook of Chiplet-Based Packaging

Dean Gonzales, AMD Analog Fellow

Abstract: Increasingly complex SoC fabrications and custom packaging are being designed to support rapid increases in compute demands, creating a landscape of expanding chiplet technologies and more diverse I/O connectivity. Signaling bandwidth increases are being met with shrinking signal-to-noise margin and modular connectorized systems for domain specific applications. This discussion will provide an overview of the SI/PI integration challenge. 

Biography:

Dean Gonzales is a Fellow Analog Engineer at AMD and is active in advanced packaging & chiplet technology development, circuit/PHY architecture, and signal integrity analysis. Prior to joining AMD, Dean worked at Broadcom and Intel and has over 25 years of experience in semiconductor and system design.


Invited Talk # 4:

High-Speed Electrical I/O Interfaces and Interconnects from 112Gbps to 224Gbps

Dr. Peng Mike Li, Intel Fellow

Abstract: This presentation will first review the challenges that high-speed electrical I/O interfaces and interconnects face, at 112 Gbps, including modulation format, transmitter and receiver architectures and circuits, channel loss (including package, PCB, and connector)/crosstalk characteristics and topologies, and then discuss how those challenges had been solved. Secondary, it will highlight the challenges when data rate increases by 2X to 224 Gbps, in the context of end-to-end I/O and interconnects, and the technologies and advancements/innovations needed in solving those challenges. 

Biography:

Dr. Peng (Mike) Li is an Intel Fellow and the technologist for high-speed I/O and interconnects at Intel Corporation. He serves as Intel’s technical expert and adviser in high-speed I/O and link technology; standards; SerDes architecture; electrical and optical signaling and interconnects; silicon photonics integration; optical field-programmable gate arrays (OFPGAs); and high-speed simulation, debug and test for jitter, noise, signaling and power integrity, from deign validation, to high-volume manufacturing (HVM). 

Li joined Intel in 2015 with the acquisition of Altera Corp., where he had held a similar role since 2012. Before joining Altera in 2007, Li spent nearly a decade at Wavecrest Corp., culminating in his seven-year tenure as chief technology officer (CTO). He began his career in 1991 as a post-doctorate researcher on high-energy astrophysics at the Space Sciences Laboratory at the University of California, Berkeley.

A distinguished scientist and technologist, Li has contributed extensively to standards during his industry career, including PCI Express, Ethernet, Optical Internetworking Forum (OIF), JEDEC, Fibre Channel, and SATA/SAS. He has also published widely, including >110 referred papers, >40 patents, five books and book chapters on jitter and high-speed architecture, testing, modeling, and analysis.

Li earned a bachelor’s degree in space physics from the University of Science and Technology of China in Hefei, China; a master’s degree in physics and a master’s degree in electrical and computer engineering, both from the University of Alabama in Huntsville (UAH); and a Ph.D. in physics, also from UAH. Li was named an IEEE Fellow in 2012, an Altera Fellow (2012), an Intel Fellow (2015), and Engineer of the year (2018, Designcon). He served as the BOD member for OIF since 2018. He has been elected as an affiliated professor at the Department of Electrical Engineering, University of Washington, Seattle, since 2010. 

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