Please see also our program on EDAS with session chair information and links to presentations (for registered attendees).
Sept. 14 - Note that all times are US Eastern Time (EDT)
08:55am - 12:15pm Tutorials
09:50 - 12:50 Industry Forum: High Speed Interconnects POSTPONED TO FRIDAY
Sept. 15 - Note that all times are US Pacific Time (PDT)
| 9:00 - 9:15am | Opening Ceremony | |
| 9:15 - 10:15am | K1: Opening Keynote Address | |
| Jan Rabaey, CTO, STCO Division, IMEC, Belgium, and Professor, EECS Dept., Univ. of California at Berkeley | ||
| "Human-Centric Computing" | ||
| 10:15 - 10:30am | Break | |
| 10:30 - 11:30am | TS1: Deep Neural Network Acceleration via FPGAs | |
| Implementation and Evaluation of a Neural Network-Based LiDAR Histogram Processing Method on FPGA | Gongbo Chen (Fraunhofer IMS, Germany); Giray Atabey Kirtiz (University of Duisburg-Essen, Germany); Christian Wiede (Fraunhofer IMS, Germany); Rainer Kokozinski (University of Duisburg-Essen, Germany) | |
| FPGA Implementation of a Reconfigurable Recurrent Neural Networks (RNN) Unit | Michael Wasef and Nader Rafla (Boise State University, USA) | |
| Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA | Mahesh M (Indian Institute of Information Technology Kottayam, India); Nalesh S (CUSAT, India); Kala S (Indian Institute of Information Technology Kottayam, India) | |
| Tufan: Low-Power Throughput Architecture for Acceleration of EfficientNet on Cloud FPGAs | Mohammadreza Baharani, Ushma Bharucha, Kaustubh Mhatre and Hamed Tabkhi (University of North Carolina at Charlotte, USA) | |
| 11:30am - 12:30pm | TS2: Future Technologies and Circuits and Energy Harvesting | |
| Optimizing Quantum Circuits for Arbitrary State Synthesis and Initialization | Naveed Mahmud, Andrew GJ MacGillivray, Manu Chaudhary and Esam El-Araby (University of Kansas, USA) | |
| Optimization of 3D Stacked Nanosheets in 5nm Gate-All-Around Transistor Technology | Anil Gundu Kumar (The Hong Kong University of Science and Technology, Hong Kong); Volkan Kursun (UST HongKong, Hong Kong) | |
| Dual-Band GSM Energy Harvester for Duty-Cycle Approach in 180nm CMOS Technology | Hugo Daniel Hernandez, Diego Augusto Pontes and Bruno Soares (Universidade Federal de Minas Gerais, Brazil); Dionísio Carvalho (University of São Paulo & USP, Brazil); Wilhelmus Van Noije (University of São Paulo, São Paulo, Brazil) | |
| Stereolithography-Based Rectenna for Wireless Energy Harvesting | Xuan Viet Linh Nguyen (INSA Lyon, France); Tony Gerges (Ampere, France); Jean-Marc Duchamp (University Grenoble Alpes & G2Elab, France); Philippe Benech (Université de Grenoble-Alpes, G2ELab, France); Jacques Verdier (Institut National des Sciences Appliquées, France); Philippe Lombard (University of Lyon, France); Michel Cabrera (Université de Lyon, France); Bruno Allard (INSA Lyon, France) | |
| 12:30 - 1:30pm | LUNCH BREAK | |
| 1:30 - 2:30pm | TS3: Novel Circuits and Analysis for Applications | |
| Software-Defined Temporal Decoupling in Virtual Platforms | Lukas Juenger, Alexander Belke and Rainer Leupers (RWTH Aachen University, Germany) | |
| Embedded ICG-Based Stroke Volume Measurement System: Comparison of Discrete-Time and Continuous-Time Architectures | Antoine Gautier (University of Lille, Junia, France) | |
| Analysis of the Sub-μA Fully Integrated NMOS LDO for Backscattering System | Puyang Zheng (Stony Brook University, USA); Xiao Sha (Stonybrook University, USA); Milutin Stanacevic (SUNY Stony Brook, USA) | |
| A SiPM Based Sensor for Nuclear Detection Applications | Shahram Hatefi Hesari (The University of Tennessee, Knoxville, USA); Nicole McFarlane (University of Tennessee, USA) | |
| 2:30 - 3:30pm | DT: Design Track Session | |
| A Design Approach to Reduce Test Time on SOC Memories | Dieu Van Dinh (NXP Semiconductor, Inc., USA); Prokash Ghosh (NXP Semiconductor Inc & Indian Institute of Technology, Bombay, India); Misal Varma (NXP Semiconductor, Inc., India) | |
| LC-Physical Unclonable Function in 3D Wireless IC for Securing the Internet of Things Devices | Jaya Dofe (California State University Fullerton, USA); Wafi Danesh (University of Missouri Kansas City, USA) | |
| Reinforcement Learning-Based Power Management Architecture | David Akselrod (Advanced Micro Devices, Canada) | |
| An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce Annotations | Rodrigue Rizk (The Center for Advanced Computer Studies, University of Louisiana at Lafayette, USA); Dominick Rizk (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Frederic Rizk (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Ashok Kumar (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Magdy Bayoumi (University of Louisiana at Lafayette, USA) | |
| A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable Function | Dominick Rizk (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Rodrigue Rizk (The Center for Advanced Computer Studies, University of Louisiana at Lafayette, USA); Frederic Rizk (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Ashok Kumar (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Magdy Bayoumi (University of Louisiana at Lafayette, USA) | |
| 3:30 - 4:30pm | PS1: Poster Session I: Circuits and Systems | |
| FLECSim-SoC: A Flexible End-To-End Co-Design Simulation Framework for System on Chips | Tim Hotfilter (Karlsruhe Institute of Technology, Germany); Julian Hoefer (Karlsruhe Institute of Technology, Germany); Fabian Kreß (Karlsruhe Institute of Technology, Germany); Fabian Kempf (Karlsruhe Institute of Technology, Germany); Juergen Becker (Karlsruhe Institute of Technology, Germany) | |
| Generating Hardware and Software for RISC-V Cores Generated with Rocket Chip Generator | Suleyman Savas (Huawei Technologies, Switzerland); Jorn Janneck (Lund University, Sweden); Endri Bezati (EPFL SCI STI MM, Switzerland) | |
| Implementation of an SoC Architecture with Built-In Safety Features | Tibor Gergely Markovits (Budapest University of Technology and Economics, Hungary); György Rácz (Budapest University of Technology and Economics, Hungary); Péter Arató (Budapest University of Technology and Economics, Hungary) | |
| Power Swapper: Approximate Functional Block Assisted Cryptosystem Security | Abhijitt Dhavlle (George Mason University, USA); Setareh Rafatirad (University of California Davis, USA); Houman Homayoun (University of California Davis, USA); Sai Manoj Pudukotai Dinakarrao (George Mason University, USA) | |
| TestQuBE: A Testbench Enhancement Methodology for Universal Serial Interfaces in Complex SoCs | Aditya Kulkarni (Samsung Semiconductor India Research, India); Ayush Singh (Samsung Semiconductor India Research, India); Sachin Waje (National Institute of Technology Karnataka, Surathkal, India); Sunil Kashide (Samsung Semiconductor India Research, India); Seonil Choi (Samsung Electronics Co. Ltd., Korea (South)) | |
| Performance Optimization of p-Channel SnO Cylindrical Thin Film Transistors (CTFT) Using 3D Modelling | Viswanath G Akkili (University of KwaZulu-Natal, South Africa); Viranjay M. Srivastava (University of KwaZuluNatal, South Africa) | |
| 1.81 kHz Relaxation Oscillator with Forward Bias Comparator and Leakage Current Compensation Based Techniques | Xiao Sha (Stonybrook University, USA); Puyang Zheng (Stony Brook University, USA); Milutin Stanacevic (SUNY Stony Brook, USA) | |
| Real-Time Framework Optimized for Low Latency Quantum Computing Experiments | Richard Gebauer (Karlsruhe Institute of Technology, Germany); Nick Karcher (Karlsruhe Institute of Technology, Germany); Jonas Hurst (Karlsruhe Institute of Technology, Germany); Marc Weber (Karlsruhe Institute of Technology, Germany); Oliver Sander (KIT, Germany) | |
| 4:30 - 5:30pm | SS2: Special Session: Challenges and Opportunities in AI and Big Data Applications | |
| Neural Network Based Branch Predictor Design for Energy Harvesting Powered Systems | Weifan Sun and Xiaojun Cai (Shandong University, China); Mengying Zhao (School of Computer Science and Technology, Shandong University, China); Zhiping Jia (Shandong University, China) | |
| Total Variation Reduction for Lossless Compression of HPC Applications | Huizhang Luo (Hunan University, China); Junqi Wang (Rutgers University at Newark, USA); Yida Li and Kenli Li (Hunan University, China) | |
| Can We Trust Machine Learning for Electronic Design Automation? | Kang Liu (Huazhong University of Science and Technology, China); Jun Zhang (NYU, USA); Benjamin Tan (New York University, USA); Dan Feng (Huazhong University of Science and Technology, China) | |
| Efficient Localization of Origins of PVC Based on Random Signal Segmentation | Dawei Li and C. Liu (South-Central University for Nationalities, China); Xiaowei Xu (Guangdong General Hospital, China) | |
Sept. 16 - Note that all times are US Pacific Time (PDT)
| 9:00-10:00am | K2: Keynote II | |
| Kaushik Roy, Distinguished Professor and Director, C-BRIC, Purdue University | ||
| “Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems” | ||
| 10:00-10:30am | BREAK | |
| 10:30 - 11:30am | TS4: Novel Workload Acceleration Techniques | |
| Design and Optimization of a Pruning-Efficient DCNN Inference Accelerator | Che-Hao Chang and Chih-Tsun Huang (National Tsing Hua University, Taiwan) | |
| Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm | Zhuoyu Chen, Pingcheng Dong, Zhuoao Li, Ruoheng Yao, Yunhao Ma, Xiwei Fang, Huanshihong Deng and Wenyue Zhang (Southern University of Science and Technology, China); Lei Chen (Pengcheng Laboratory, China); Fengwei An (Southern University of Science and Technology, China) | |
| On Reduction of Computations for Threshold Function Identification | Wen-Chih Hsu, Chia-Chun Lin and Yi-Ting Li (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan) | |
| 11:30am - 12:30pm | TS5: Novel Techniques for Secruity and Resilency | |
| Key-Based Obfuscation Using HT-Like Trigger Circuit for 128-Bit AES Hardware IP Core | Surbhi Chhabra and Kusum Lata (The LNM Institute of Information Technology, Jaipur, India) | |
| Identifying Specious LUTs for Satisfiability Don't Care Trojan Detection | Lingjuan Wu (Huazhong Agricultural University, China); Xuefei Li, Jiacheng Zhu, Jian Zheng and Wei Hu (Northwestern Polytechnical University, China) | |
| ReCPE: A PE for Reconfigurable Lightweight Cryptography | Jeff Anderson (The George Washington University, USA); Yousra Alkabani (Halmstad University, Sweden); Tarek El-Ghazawi (The George Washington University, USA) | |
| RARES: Runtime Attack Resilient Embedded System Design Using Verified Proof-Of-Execution | Avani Dave (University of Maryland, Baltimore County, USA & UMBC, USA) | |
| 12:30 - 1:30pm | LUNCH BREAK | |
| 1:30 - 2:30pm | TS6: Advanced Power, Noise and Reliability Analysis | |
| Dynamic Power Analysis of Standard-Cell FPGA Fabrics | Bo Bao and Jason Anderson (University of Toronto, Canada) | |
| Crosstalk Noise Based Configurable Computing: A New Paradigm for Digital Electronics | Md Arif Iqbal (University of Missouri Kansas City, USA); Naveen Macha (NVIDIA Corporation, USA); Bhavana Repalle (Intel Corporation, USA); Sehtab Hossain (University of Missouri Kansas City, USA); Mostafizur Rahman (University of Missouri-Kansas City, USA) | |
| A Framework for Evaluation of Debug Path Performance in SoC | Prokash Ghosh (NXP Semiconductor Inc & Indian Institute of Technology, Bombay, India); Khwahish Sinha (NXP Semiconductor Inc, India) | |
| On the Stability, Transient and Quiescent Current Control of One Low-Voltage Class-AB Op-Amp Architecture | Aniruddha Roy, Khyati Bansal and Nitin Agarwal (Texas Instruments, India) | |
| 2:30 - 3:30pm | SS1: Special Session: Hardware Security | |
| Analog-Inspired Hardware Security: A Low-Energy Solution for IoT Trusted Communications | Samuel D Ellicott (The Ohio State University, USA); Yu Qi (Case Western Reserve University, USA); Michael Kines (The Ohio State University, USA); Abdullah Kurtoglu (Case Western Reserve University, USA); Waleed Khalil (The Ohio State University, USA); Hossein Lavasani (Case Western Reserve University, USA) | |
| LDO-Based Odometer to Combat IC Recycling | Rabin Y Acharya and Domenic Forte (University of Florida, USA); Michael Levin (Honeywell Aerospace, USA) | |
| Saidoyoki: Evaluating Side-Channel Leakage in Pre- and Post-Silicon Setting | Pantea Kiaei, Zhenyuan Liu and Ramazan Kaan Eren (Worcester Polytechnic Institute, USA); Yuan Yao (Virginia Tech, USA); Patrick Schaumont (Worcester Polytechnic Institute, USA) | |
| Distributed On-Chip Power Supply for Security Enhancement in Multicore NoC | Xingye Liu and Paul Ampadu (Virginia Tech, USA) | |
| 3:30 - 4:30pm | PS2: Poster Session II | |
| A Two-Stage Path Planning Engine for Robot Navigation System | Yu-En Hsu (National Yang Ming Chiao Tung University, Taiwan) | |
| An IMU-Aided Fitness System | Yi-Ting Lin, Chun-Jui Chen and Pei-Yi Kuo (National Tsing Hua University, Taiwan); Si-Huei Lee (Taipei Veterans General Hospital, Taiwan); Chia-Chun Lin, Yun-Ju Lee and Yi-Ting Li (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan) | |
| Cluster Tool Performance Analysis Using Graph Database | Shiuan-Hau Huang and Hsin-Ping Yen (National Tsing Hua University, Taiwan); Yan-Hsiu Liu, Kuang-Hsien Tseng and Ji-Fu Kung (United Microelectronics Corporation, Taiwan); Chia-Chun Lin and Yi-Ting Li (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan) | |
| NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators | Melvin E. Galicia (RWTH Aachen University, Germany); Ali BanaGozar (Eindhoven University of Technology, The Netherlands); Karl J. X. Sturm and Felix Staudigl (RWTH Aachen University, Germany); Sander Stuijk (Eindhoven University of Technology, The Netherlands); Henk Corporaal (Technical University Eindhoven, The Netherlands); Rainer Leupers (RWTH Aachen University, Germany) | |
| FPNA: A Reconfigurable Accelerator for AI Inference at the Edge | Peter Gadfort and Oluseyi Ayorinde (DEVCOM Army Research Laboratory, USA) | |
| Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems | Nidhi Anantharajaiah (Karlsruhe Institute of Technology, Germany); Felix Knopf (Karlsruhe Institute for Technology, Germany); Juergen Becker (Karlsruhe Institute of Technology, Germany) | |
| Design Study on Impact of Memory Access Parallelism for Cloud FPGAs | Arnab Ardhendu Purkayastha and Hamed Tabkhi (University of North Carolina at Charlotte, USA) | |
| Combined Side-Channel Attacks on a Lightweight Prince Cipher Implementation | Soner Seckiner and Selcuk Köse (University of Rochester, USA) | |
| GPU-Based Acceleration of Fully Parallel Annealing Algorithm for Combinatorial Optimization | Kazushi Kawamura, Kaisei Okawa, Gregory Gutmann, Thiem Chu, Jaehoon Yu and Masato Motomura (Tokyo Institute of Technology, Japan) | |
| 4:30 - 5:15pm | SS3: Special Session: Hardware Design for Deep Neural Networks | |
| A Convolutional Neural Network on Chip Design Methodology for CNN Hardware Implementation | Kun-Chih Chen, Yi-Sheng Liao and Cheng-Kang Tsai (National Sun Yat-Sen University, Taiwan) | |
| Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults | Jin-Fu Li and Yung-Yu Tsai (National Central University, Taiwan) | |
| A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks | Yu-Guang Chen, Chi-Wei Hsu, Hung-Yi Chiang, Tsung-Han Hsieh and Jing-Yang Jou (National Central University, Taiwan) | |
| 5:15 - 5:30pm | Closing Remarks | |
Sept. 17 - Note that the times below are US Eastern Time (EDT)
09:50am - 12:50pm Industry Forum: High Speed Interconnects (virtual only)
